AMD FPGA series - #1 Running ISE on Widows, Linux, and Docker

Welcome to the blog post of the AMD FPGA video series.

When I was at my parents’ house a couple of months ago, I dug out my very first FPGA board. A digilent board with a Spartan 3 FPGA. It was the first time you could get a decent size FPGA board for a price affordable for a student back in 2004.

The Spartan 3 FPGA is not supported by Vivado, but only by ISE. The last time that I used ISE was in 2021 for programming a client’s board with a Spartan 6. Back then I tried with the ISE virtual machine provided by AMD, but I couldn’t program the FPGA with the Platform Cable. At the end I used my old Windows 7 notebook that was the machine used to develop the FPGA for the project in 2014.

I have decided to go back and test how it is possible to use ISE for generating the bitstream and downloading it to the FPGA on current versions of Windows and Linux without the virtual machine provided by AMD.

I am also going to show you how to install ISE in a docker container.

Full disclaimer: this video is not sponsored by Digilent nor AMD and the JTAG cable has been bought by Starware Design.

Continue Reading

Microchip Polarfire SoC series - #3 Custom IP

Welcome to the blog post number 3 in the Microchip PolarFire SoC series! 

Today, we’re integrating a custom IP into the PolarFire SoC video kit’s base design, addressing a key aspect of practical FPGA development. We’re going to add the system version IP that I have created for the FPGA meets devops video series, but this time the bus interface is APB instead of AXI. A simple testbench written in Python and cocoTB is used to validate the IP. And we’re going to add the system version application to the Linux image with a custom meta layer.

In this blog post, I assume you’ve watched the first two videos of the Microchip Polarfire SoC series where I explained how to install the tools, build the Yocto image, etc.

Full disclaimer: this video is not sponsored by Microchip and the video kit has been bought by Starware Design.

Continue Reading

FPGA meets DevOps - Simulation with Cocotb

In the previous blog postwe integrated Vivado with GitLab CI to automatically build the FPGA bitstream.

What about simulation? In this video I am going to show you how to run and debug cocotb test cases locally and then how to run them with Gitlab CI.

Continue Reading

Microchip Polarfire SoC series - #2 Basic design

Welcome to the blog post number 2 in the Microchip PolarFire SoC series! Today, we’re creating a basic design for the PolarFire SoC video kit from scratch. While in the previous blog post we’ve seen how to build the reference design, it is important to be able to create a design from scratch. Until you do, you might miss some important details.

We’re going to create a custom MSS configuration and an FPGA design with two GPIO banks connected to the LEDs and dip switches on the video kit.

We’re going to add support for the GPIO banks to the Linux kernel, and write some examples in Python for testing.

I assume you’ve read the first blog post of the Microchip Polarfire SoC series since I did explain about how to install the tools, build the HSS firmware, Yocto image, etc.

Full disclaimer: this video is not sponsored by Microchip and the video kit has been bought by Starware Design.

Continue Reading