AMD FPGA series - #1 Running ISE on Widows, Linux, and Docker
Welcome to the blog post of the AMD FPGA video series.
When I was at my parents’ house a couple of months ago, I dug out my very first FPGA board. A digilent board with a Spartan 3 FPGA. It was the first time you could get a decent size FPGA board for a price affordable for a student back in 2004.
The Spartan 3 FPGA is not supported by Vivado, but only by ISE. The last time that I used ISE was in 2021 for programming a client’s board with a Spartan 6. Back then I tried with the ISE virtual machine provided by AMD, but I couldn’t program the FPGA with the Platform Cable. At the end I used my old Windows 7 notebook that was the machine used to develop the FPGA for the project in 2014.
I have decided to go back and test how it is possible to use ISE for generating the bitstream and downloading it to the FPGA on current versions of Windows and Linux without the virtual machine provided by AMD.
I am also going to show you how to install ISE in a docker container.
Full disclaimer: this video is not sponsored by Digilent nor AMD and the JTAG cable has been bought by Starware Design.
Video
You can find this blog post in video format on YouTube (embedded below).
Hardware
We are going to use the digilent Spartan3 starter kit and the HS2 JTAG cable also from digilent. The original JTAG cable used the parallel port so I got a HS2 JTAG cable which has a USB interface.
It is a low cost solution (about 64 USD) that supports I/O voltages up to 5V and it is compatible with both ISE and Vivado.
The board centres around the Spartan 3 200 FPGA. To store the bitstream, back then you had to use a specific flash device from xilinx, called platform flash. With the Spartan 3A and 3E series onwards, Xilinx introduced the possibility of using standard SPI flash even if limited to a few vendors.
On top of the usual LEDs, display, and switches, it has 1Mbytes of static RAM to be used with a microcontroller soft core like Microblaze. Even if it is more expensive, static RAM has the advantage compared to dynamic RAM that it doesn’t need a memory controller in the FPGA.
Other I/Os include a serial port, VGA and PS/2 used for keyboard and mouse before USB. For JTAG there are 2 connectors, the standard 14 pins, 2 rows, 2mm pitch connector and a 6 pins, one row, 2.54mm pitch connector.
We’re going to build one of the examples provided by digilent.
Windows 10/11
Download the complete installation file. I am going to download the archive that has both Linux and Windows versions since we’re going to install ISE on Linux and also we’re going to create a Docker container with ISE.
Extract the archive and run xsetup. Select the webpack version, check the install the drivers option and uncheck the getting the license option.
You are going to need a license file even for the webpack version. You can get it from the AMD licensing website. If the installer gets stuck, terminate the webtalk program.
What we do next depends on the Windows version.
Windows 10
If you’re using Windows 10, it is quite easy. Once the installation has completed, we need to rename and copy a couple of DLLs. I found these notes in the EEVBlog forum.
Navigate to C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64 (adjust it based on where you have installed ISE). Locate libPortability.dll and rename it to libPortability.dll.orig (as a backup).
Find libPortabilityNOSH.dll in the same folder, make a copy, and rename the copy to libPortability.dll. Repeat for the Common Library Folder C:\Xilinx\14.7\ISE_DS\common\lib\nt64.
Windows 11
If you’re using Windows 11, instead of copying the dll, you need to replace it with a modified version from you can download here .
Also you need to set this environment variable XILINX_VC_CHECK_NOOP and set it to false. Reboot your PC for the changes to take effect.
Now let’s start project navigator and point to the license file downloaded from the AMD licensing website. And we can rebuild the reference design from digilent.
Open impact, double click on boundary scan and init the scan chain. Add the bitstream and program the FPGA.
And that’s it for Windows. It is very easy to get ISE working on Windows 10 native without a virtual machine and the digilent JTAG cable works perfectly. On Windows 11 it requires a few extra steps, but still quite easy.
Linux
I am going to install ISE on Ubuntu 22 LTS. I am re-using the software archive and the licence from the Windows installation.
Install the following library
sudo apt install libncurses5
Extract the archive and run xsetup as root. Select the webpack installation, but on Linux don’t install the drivers. Unfortunately I wasn’t able to get the drivers to build on Linux, the current kernel and the one used back when ISE 14.7 was released are too different. We’re going to use the digilent tools instead.
Before doing that, let’s configure the licensing and build the reference design.
As said earlier, I wasn’t able to get the drivers for the JTAG cable working, even if the digilent drivers were installed correctly. I assume that if you’re using an FPGA that is only supported by ISE, the project is in the maintenance phase and not in active development. In that case, using the digilent tools seems like a reasonable compromise. Unfortunately this means it is not possible to use Chipscope.
Download the adapt runtime and utilities and install them:
$ sudo dpkg -i digilent.adept.runtime_2.27.9-amd64.deb
$ sudo dpkg -i digilent.adept.utilities_2.7.1-amd64.deb
Check that we can see the JTAG cable
$ djtgcfg enum
Found 1 device(s)
Device: JtagHs2
Device Transport Type: 00020001 (USB)
Product Name: Digilent JTAG-HS2
User Name: JtagHs2
Serial Number: xxxxxxx
And scan the JTAG chain
$ djtgcfg -d JtagHs2 init
Initializing scan chain...
Found Device ID: 05045093
Found Device ID: 01414093
Found 2 device(s):
Device 0: XC3S200
Device 1: XCF02S
Now program the FPGA
$ djtgcfg -d JtagHs2 -f S3demo.bit -i 0 prog
WARNING: startup clock for this file is 'CCLK' instead of 'JTAG CLK'.
Problems will likely occur. Associate config file with device anyway (Y or N)? [N] y
Programming device. Do not touch your board. This may take a few minutes...
Programming succeeded.
Docker
I have created a docker file to run the ISE tools as part of a continuous integration pipeline as shown in the FPGA meets devops video series.
The docker file is a mix of the docker file I have created for Vivado and one that I found on the web here.
Clone the repository
$ git clone https://github.com/starwaredesign/ise-docker.git
$ cd docker-ise
Copy the license file and make sure it is named Xilinx.lic.
Like in the third FPGA meets devops video, run a webserver where you have downloaded the complete ISE archive:
$ python3 -m http.server
Serving HTTP on 0.0.0.0 port 8000 (http://0.0.0.0:8000/) …
Then create the docker container using this command line and replace the IP address with the one from your machine
docker build --build-arg ISE_HOST=192.168.1.196:8000 -t ise .
We can check that we can run the ISE command line tools
docker container run -it ise bash
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